This invention relates to programmable logic devices (PLDs) and more particularly to an improved interconnect architecture for such devices.
Programable Logic Devices (PLDs) are a widely used form of integrated circuit due to the flexibility provided by their customizable nature. In general PLDs include field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), simple programmable logic devices and laser programmable devices. Architecturally a PLD includes logic blocks and input/output (I/O) blocks, which are connectable through a programmable interconnect structure or network.
A typical PLD is an integrated circuit chip that, wholly or in part, consists of an array of one or more logic blocks, I/O and a programmable routing or interconnect network that can be programmed by a user to provide an interconnection between the logic blocks and I/O circuits to achieve a desired logic function. The PLD can be a standalone device or be embedded in a larger integrated circuit such as ASICs or the like. Exemplary forms of such devices are disclosed in U.S. Pat. No. 5,825,202 and U.S. Pat. No. 5,687,325.
The logic blocks may be comprised of a fixed logic function or may in turn also have programable interconnections or functionality. The logic blocks may be further broken down as sub-blocks or grouped together as a cluster of blocks. The blocks may also include input/output circuits. Typically the I/O circuits enable connection of the chip to external circuits or to other parts of the chip as in the case of embedded FPGAs. The I/O blocks are typically arranged at the periphery of a chip. A PLD is normally arranged as a regular array of logic blocks each of which may be identical or may be of several different types such as RAM blocks, Look-Up-Table based blocks, P-term based blocks etc. The conductors of the programmable interconnect network array are typically arranged along rows and columns defined by the array of logic blocks as shown schematically in FIG. 1.
The interconnect structure of the PLD consists of pre-fabricated wires and pre-fabricated switches which can be programmed to electrically connect different logic blocks to provide a desired function. The connections between the conductors (wires) and the logic blocks and between different wire segments is implemented by means of programmable switches at predetermined interconnection points. The programmable switches may be implemented as pass-transistors, tri-state buffers, fuses, antifises or combinations thereof. Laser programing of interconnections may also be achieved by burning off the metal conductors at desired locations. In some cases a switch state can be controlled by a Static or Dynamic Random Access Memory (SRAM or DRAM), Read Only Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable and Programmable Read Only Memories (EEPROMs), Flash memory or any other variation or combination of the above memory. Various types of switches are well known in the art and are described for example in U.S. Pat. No. 4,870,302 and U.S. Pat. No. 5,955,751 to list a few.
There are a number of tradeoffs involved in the design of PLDs. A PLD designer or architect is constrained by various operational parameters such as speed of circuits implemented in the PLD, semiconductor or silicon area required for a given logic capacity, power dissipation of the PLD once it has been programmed by a user, reliability (e.g. low glitch probability) and routing flexibility. A PLD architect cannot know before hand all the many uses for which a user may program the device. Thus PLDs are designed to be as general as possible.
For example, a PLD architect""s objective may be to minimize the surface area of the PLD while maximizing the logic capacity. That is, maximize the number of and functionality of logic blocks and provide sufficient interconnect resources and flexibility to allow as broad a range of circuit implementations as possible. Another design objective may be to maximize the speed of circuits implemented in the PLD while minimizing the surface area, logic and interconnect resources required to implement the circuits. For example, a PLD architect knows that speed can be improved by reducing the number of programmable connection switches, but this comes at the expense of routing flexibility. Reliability, in terms of glitch prevention can be improved by spacing interconnect wires further apart, but this comes at the expense of area.
Consequently, one area of focus in PLD architecture design is the interconnect network architecture, where the objective is to minimize the surface area required for the interconnect resources while maximizing the speed and minimizing the PLD resources required to implement circuits on the PLD. The interconnect architecture here refers to interconnect conductors, the programmable switches and the interface between them and the logic blocks. The reader is referred to U.S. Pat. No. 5,907,248, which provides a background on various interconnection architectures and improvements thereto.
However, circuits that are implemented in PLDs tend to have different parts with different requirements. For example, some critical paths of the circuit have to be fast to meet timing requirements, some parts (e.g. clock signals) need to be glitch free and parts which are not speed sensitive should use as little silicon area or PLD resources as possible.
Most PLD architectures do not take into account this circuit heterogeneity. Most of the prior ant use a homogenous interconnection architecture wherein parameters such as wire widths, spacing between wires, dimensions of the transistors used in the buffets and switches, interface circuits between the wires/switches and the logic blocks are constant throughout the PLD. Furthermore homogenous architectures are easier for the CAD tools that are used to map circuit descriptions into the PLD architecture.
Current interconnect architectures have considered varying a single parameter in order to optimize the PLD. For example Actel""s U.S. Pat. No. 5,073,729, Altera""s U.S. Pat. No. 5,900,743 and Xilinx U.S. Pat. No.""s 5,801,546 and U.S. Pat. No. 5,907,248, describe PLD architectures in which optimization is limited to using different lengths of interconnect wires. On the other hand, U.S. Pat. No. 5,942,913 describes an interconnect structure using a mixture of buffered and unbuffered interconnect lines. In both cases, optimization is limited to just one parameter.
However, these architectures are limited in that they do not offer a user sufficient flexibility when designing a circuit that requires different PLD interconnect resources for different parts of the circuit. For example in U.S. Patent No. 5,900,743 horizontal conductors of many different lengths makes it possible to make interconnections between horizontally aligned logic regions using conductors that are close to the appropriate lengths for making that connection.
Accordingly there is a need for an improved PLD architecture that is optimised in terms of one or more selected operational parameters such as speed, power, area, flexibility and reliability, while minimizing the impact on the remaining parameters.
An advantage of the present invention is the provision of a PLD architecture that is optimized for a selected one or more operational parameters, while minimizing the impact on the remaining parameters. For example the operational parameters may include speed, area, power, reliability and flexibility.
In accordance with this invention there is provided a PLD comprising:
(a) one or more function blocks; and
(b) a plurality of groups of interconnect resources each group of a selected type for programmable connection to one or more of the function blocks, and wherein a first number of at least one type of interconnect resources being optimized for a first operational parameter of the PLD and a second number of the same type being optimized for a second operational parameter.
In a further embodiment of the invention the function blocks are logic blocks.
In another embodiment of the invention the function blocks are input/output circuits.
In one embodiment the interconnect resource includes a plurality of interconnect conductors (or wires) wherein a first number of conductors is selected to have spacing between adjacent conductors that are less than that of the spacing between conductors of a second number of conductors. For example, portions of wires may be spaced at one unit and three units apart. The wires that are spaced further apart will have much lower coupling capacitances than the wires spaced closely together. The lower coupling capacitance reduces the signal delay through the wires, increasing the achievable speeds of circuits implemented in the PLD. The wires that are spaced closer together occupy less area, and are thus optimized for area.
In a further embodiment the interconnect resources includes a plurality of interconnect conductors wherein a first number is selected to have conductor widths that are different compared to the conductors widths of a second number or conductors. The wires that have larger widths have reduced resistance, which leads to increased speed, particularly for long wires. The wires with the narrower widths occupy less area.
In a further embodiment the interconnect resource includes a group of interconnect conductors (or wires) wherein a portion of the routing wires are connected by switches of a first size and a second portion of the wires are connected by switches of a second size. The switches with larger dimension have increased drive strength, which decreases the time required to charge and discharge the routing wire capacitance. The net result is increased speed. The smaller switches, although slower, occupy less area. In a preferred embodiment the switch is composed of pass transistors. In an alternate embodiment the switch is composed of tri-state buffers, and a speed advantage can be achieved through larger transistors or by changing the number of stages (buffer sub-blocks) in the tri-state buffer.
In a further embodiment, the interconnect resource includes a plurality of multiplexers or tri-state buffer switches for coupling to the interconnect conductors (or wires) wherein a first number of the multiplexer or tri-state buffers have a different circuit topology than or a second number or multiplexer or tri-state buffers. In a preferred embodiment, the multiplexer or tri-state buffer switches have a circuit topology that yields the highest speed for some switches, and a topology that is most area-efficient for other switches. For example, a 16:1 multiplexer can be implemented as sixteen independent pass transistors (a single-stage 16:1 multiplexer) or as a set of 2:1 multiplexers cascaded together in four (4) stages. The single-stage 16:1 multiplexer would have better speed, but requires a larger area.
In a further embodiment, the interconnect resource includes a plurality of programmable switches for connecting the interconnect conductors (or wires) to the logic block input or outputs or for connecting two different interconnect conductor segments, and wherein a first number of the wires have fewer routing switches connected to them (hence smaller capacitive load on them, hence faster) and a second number of the wires have a larger number of switches connected to them. Thus, by reducing the number of routing switches connecting to some of the wires, the capacitance load on the wires is reduce. For example, some wires may have twenty (20) programmable switches which can drive them, while others may have only ten (10). The wires which can be driven by fewer switches, will have higher speed, because they have less parasitic loading due to switches, and they will require less switch area per wire. By reducing the number of switches that can connect to only some of the routing wires, a gain in speed of more lightly loaded wires is made without reducing the flexibility of the PLD. As well, it is also often possible to gain area savings by reducing the number of switches on only some of the wires in this manner.
In a still further embodiment, the interconnect resources includes a plurality of routing wires with a portion of the wires having extra-fast paths into logic blocks or I/O blocks and the second portion having more flexible routing. This may be implemented with multiplexers coupled between routing wires and logic block (or I/O block) input pins in an unbalanced tree topology.
In a still further embodiment, the interconnect resource includes two types of input pins at the interface between the logic block input and the interconnect wires. One set of input pins is optimized for speed and the other for routing flexibility. By having the extra fist wires connect to special input pins on the logic blocks, these input pins can be driven by a smaller number of routing wires, and hence have smaller (and faster) multiplexers between them and the routing wires. The second group of pins will be driven by a larger number of routing wires, hence allowing a larger number of wires to connect to the logic block, hence improving PLD flexibility.
In a still further embodiment, the interconnect resources includes two different types of buffers at the interface between the logic block or I/O block output and the interconnect wires. Each output pin is connected to two groups of buffers. One group of buffers has lower intrinsic delay by virtue of having fewer stages and lower overall delay by virtue of having fewer interconnect wires that can be connected to it. The second group has more programable switches loading it, hence it is slower, but has higher routing flexibility. The net effect is that speed critical connections can use the faster, but less flexible, group of buffers, while the non-speed-critical connections can use the slower more flexible group of buffers. As a result, the speed of a circuit implemented in the PLD is enhanced while routing flexibility is maintained.
In another embodiment the PLD includes a number of wires having either increased spacing between the wires or including a grounded shield wire between them or by using differential signaling for reducing unwanted transitions or glitches on the wires. The other wires use a smaller spacing and no shield wires and hence are optimized for area.
In a further embodiment of the invention, a given type of interconnect resource may be optimized for two or more operational parameters.
In a further embodiment, two or more different types of interconnect resources may each be optimized for two or more operational parameters.